IBM Creates World’s Fastest Transistor Using Graphene
By on April 13th, 2011

IBM on Tuesday, 12th April, announced that they have made the world’s fastest transistor using graphene and also hinted that they might go into commercial production very soon. This is major news, as graphene might revolutionize the current semi-conductor industry scenario. Graphene may even be good enough to replace silicon, the standard material used in all of today’s semi-conductor devices, in the near future.

What is Graphene? How is it produced?

Graphene is a mono-layer of carbon, with the atoms in hexagonal configuration. Each of the carbon atoms has bonds with three neighboring carbon atoms, maintaining, what is called, a sp2 hybridization. Basically, it is one layer of graphite.

Graphite Structure

The Structure of Graphite

It is produced in the most mundane way you can think of. A pure crystal of graphite is repeatedly stripped off using Scotch Tape, until, about 50 or more repetitions later, graphene is found buried amongst poly- or bi-layered graphite (Pic below). This has to be verified, and can be done so optically, after the extracted graphene is mounted on a Silicon Dioxide (SiO2) substrate of correct thickness. Often, Raman spectroscopy is used for verification.

Graphene under light

How Graphene looks under light and the right thickness of Si layer. (Courtesy: Graphene Industries)

Other methods, which allow graphene to be grown for commercial purposes, are also known. Primary among these is Chemical Vapour Deposition (CVD), in which carbon vapour (obtained from carbon rich substances like acetylene) is deposited on a Ni or Cu substrate.


How did IBM do it?

Graphene grown directly on a SiO2 substrate suffers from the problem of scattering of electrons, resulting in the deterioration of the transport properties and also producing non-uniformity across the SiO2 wafer. The IBM team used a novel substrate called Diamond-like Carbon’ (DLC) on top of the SiO2 layer so as to reduce the scattering. DLC is loosely amorphous (i.e. powdered) diamond. It has all atoms in sp3 configuration (i.e. each atom bonds to four neighbors) and tetrahedral arrangement, but, being a powder, lacks any fracture planes. Thus, having the necessary properties of diamond, it is also flexible and can easily be used as a coating over a substrate.

Graphene couples weakly to the DLC layer and this greatly reduces the scattering, as also the temperature dependence of the material. In fact, the transport properties of DLC-grown graphene remains almost (maybe, exactly) temperature independent right up to 4.3K (which is minus 269 Centigrade).

The IBM team took graphene, made using CVD on a Cu layer, and, after protecting with polymethylmethacrylate (PMMA), dissolved the Cu layer using FeCl3. Then, the PMMA-graphene was transferred to a DLC layer on the SiO2 substrate and the PMMA was got rid of. Raman spectroscopy was used to verify the quality of the graphene layer.

Graphene lends itself readily to fabrication of Field Effect Transistors (FETs). By constructing the gate, drain and source contacts using pure metal and properly calibrating their device, the IBM team achieved input-output characteristics similar to a Si FET. Further, they achieved very high switching speeds up to 26 GHz for a 550 nm long device.


Arrangement of a FET Graphene transistor

Schematic representation of a graphene FET (Courtesy: Nature)

What a graphene transistor actually looks like

How will it score over Si transistors?

Graphene transistors will be ideal in radio frequency (RF) range signals, due to their high switching speeds. Unlike Si transistors, their properties don’t degrade at low temperatures. This means that there will be no unnatural change in transport properties as the temperature is varied.

The problem graphene transistors have is that they have low on-off voltage ratio. However, that is not a very strict condition for RF communication. A more serious problem is that of high contact resistance, which cannot be minimized, unlike MOSFET‘s in case of Si.



IBM reports that transistors with cut-off frequencies (the frequency at which the current gain becomes unity) as high as 155 GHz have been achieved on a 40 nm device using short gate lengths.

A figure of merit is the product of cut-off frequency and gate length. IBM reports the figure of 13 GHz mm for the 550 nm device, which beats the highest value of 9 GHz mm for Si MOSFETS by a long margin.

The future may be here already.


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Author: Debjyoti Bardhan Google Profile for Debjyoti Bardhan
Is a science geek, currently pursuing some sort of a degree (called a PhD) in Physics at TIFR, Mumbai. An enthusiastic but useless amateur photographer, his most favourite activity is simply lazing around. He is interested in all things interesting and scientific.

Debjyoti Bardhan has written and can be contacted at

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