ARM has announced it’s new Two Cortex A9 MPCore hard macro implementations for the TSMC 40nm-G processors, which empowers companies to make high-performance, low-power Cortex-A9 processor-based devices(Smartphones and MIDs). This hard macro implementation will enable devices to operate at frequencies greater than 2GHz easily.
This development is the result of ARM’s interest in advanced physical IP together with processor and fabric IP technology, and leading-edge implementation flows from the EDA industry.
Advanced physical IP techniques have enabled critical circuits within the design to be replaced with highly tuned logic cells and memories, increasing performance while lowering overall power consumption.
Both ARM dual core Cortex-A9 hard macros will share a common seven-power domain, dual-NEON technology configuration supporting SMP (symmetrical multiprocessing) operating systems with up to 8MB of Level2 cache memory and will be delivered with all scripts, vectors and libraries required to integrate the macro directly within any SoC device.
All technicalities aside, this is great news for us users because it promises us great power-packed times ahead.